25 Sep

Staff Design Implementation Engineer Jobs Vacancy in Microsemi Bayan Baru

Position
Staff Design Implementation Engineer
Company
Microsemi
Location
Bayan Baru M07
Opening
25 Sep, 2018 30+ days ago

Microsemi Bayan Baru urgently required following position for Staff Design Implementation Engineer. Please read this job advertisement carefully before apply. There are some qualifications, experience and skills requirement that the employers require. Does your career history fit these requirements? Ensure you understand the role you are applying for and that it is suited to your skills and qualifications.

Follow the online directions, complete all the necessary fields, and provide all relevant information so your application is submitted correctly. When you click the 'Apply this Job' button (open in new window) you will be taken to the online application form. Here you will be asked to provide personal and contact details, respond to employment-related questions, and show how you meet the key selection criteria.

Staff Design Implementation Engineer Jobs Vacancy in Microsemi Bayan Baru Jobs Details:

The Engineering Services group is responsible for creating the design of a device by providing technical expertise through cutting edge design tools and technology. This group work closely with various business unit product development teams to ensure the design is physically realizable.

As a Design Implementation engineer, the candidate will be supervised by a local manager, be engaged into projects to perform the synthesis, DFT implementation, timing closure and ensure the design is implemented correctly with various checks/verification/audit. Also, be involved in design flow/methodology definition and development to ensure the design team is always using best-in-class design methodology.

Responsibilities:

  • Own macro level and potentially system level functional modules and implement the macros to high quality standard
  • Implement plans to synthesize, implement Design-For-Test (DFT) and close timing on complex digital integrated circuits at the block, subsystem or device level (100K to 10M+ gates) which are coded in VHDL/Verilog.
  • Work with various design groups across different disciplines (Logic, Circuits, DFT & Layout) to meet timing closure, area, power, and performance requirements.
  • Design, implement and maintain synthesis, DFT and Static Timing Analysis scripts using best-in-class methodologies.
  • Analyze log and report files to ensure the tools are getting the required results and make adjustments to the scripts to get the required results within the scheduled milestones.
  • Communicate regularly with the project teams world-wide to resolve issues and to ensure meeting targeted goals and schedule.
  • Provide/propose new/enhance synthesis, DFT and STA flow and methodology to reduce the development TAT to meet product requirements

This position requires at least BSEE with 5-10 years of ASIC development experience in a fast paced environment. You are required to have expertise in a wide range of areas in design implementation, tools and flows:

  • BEng/MEng in EE or Computer Science with the completion of several complex ASIC or IC tapeouts in VDSM process technology nodes.
  • Design and Synthesis experience in high performance design (high speed / low power) is a must. State of the art knowledge of semi-custom design implementation tool.
  • Experienced with tools and methodologies for Synthesis - hierarchical synthesis, DFT handling, retiming, clock gating, logic restructuring, optimization and Logic Equivalency Check
  • Experience in synthesis algorithms, best RTL coding for synthesis, low-power and high-speed design trade-offs, 'physical aware' synthesis, deep sub-micron process effects
  • Understand Design-For-Test tools (Tetramax, DFT Advisor) & methodologies (Scan chains, ATPG, BIST, Fault models, Fault Coverage and generation).
  • Understand JTAG IEEE standard for board level connections testing and/or enable block level DFT testing is a plus.
  • Experienced in Static Timing Analysis tools/flows (e.g. Prime Time, Extreme DA Gold Time or equivalent) and constraint checkers.
  • Good scripting skills in Perl, TCL and Shell, particularly in synthesis & timing algorithms, with solid understanding of UNIX/LINUX.
  • Working knowledge of RTL coding
  • Low power methodologies and impact on overall design goals.
  • Able to work autonomously as well as in a team environment across multiple geographical sites, with a strong desire to succeed.
  • Excellent debugging, problem solving and analytical skills.
  • Excellent verbal and written communication skills. Strong interpersonal skills.
  • Have lead and mentor others and work under challenging environment.


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  • Company: Intel
  • Added: 9 days ago